1. Field of the Invention
This invention relates to MEMS-based, computer systems, clock generation and oscillator circuits and LC-tank apparatus for use therein.
2. Background Art
Oscillators serve a variety of purposes in electronic systems and integrated circuits. For example, in RF systems, oscillators are typically used for frequency translation, via mixing, to and from low and high frequencies, or the baseband and passband, respectively. In mixed-signal circuits, such as switched capacitor circuits, a clock is required to open and close the switches within specific intervals. In microcontrollers, oscillators set the time base, or clock, of the system, which paces the execution of instructions in the core.
Currently clock and other periodic signals are synthesized with components apart, or off-chip, from the electronics they support. Current embodiments of periodic signal synthesis include a quartz crystal reference for an on-chip oscillator that drives a phase locked loop (PLL) or delay locked loop (DLL) which is utilized to generate the frequency, or frequencies, needed for the application. Quartz crystals are utilized as they provide a highly stable reference for frequency synthesis. However, the technology is incompatible with silicon integrated circuit technology. If clock synthesis could be performed on-chip, with no external components, significant reductions in power dissipation, size, and cost of electronic systems and integrated circuits could be realized. In fact, for some low-performance processors, the cost of the crystal reference itself can exceed the cost of the entire processor. Size reductions could be realized if the reference oscillator were integrated onto the processor die, and thus, the area allocated on the printed circuit board for a discrete reference would be eliminated. Moreover, a reduction in the pad count could be realized on the processor die as an interface to the reference electronics would no longer be required. Power dissipation could be reduced by as much as two orders of magnitude, dependent on clock frequency, because power hungry inter-chip transceivers would not be required. Lastly, with the use of a discrete clock reference comes the requirement of a PLL or DLL for frequency generation as crystal-based oscillators are fixed-frequency. These subsystems, though typically integrated, can add significantly to the overall power budget.
Despite the obvious and inherent advantages of integrated clock synthesis, the development of such technology has not gained much momentum. The challenges faced are many and include the inability to generate a stable clock signal on-chip due to unavailable or poor on-chip reference technology, temperature instability, and drift. Stability is the foremost factor limiting ubiquitous employment of monolithic clock references, since short term instability can cut into processor timing budgets and compromise performance.
Phase Noise and Jitter
Oscillators are designed to provide a stable output frequency that ideally does not deviate from some center frequency, typically referred to as fo. In the frequency domain, this performance can be represented by a Dirac-Delta function at fo. However, due to device noise such as flicker and thermal noise, as well as electromagnetic interference, oscillators will deviate from this center frequency. Thus, finite power exists in frequencies around the center frequency. Minimizing this phenomenon is highly desired since it can cause a variety of problems such as reciprocal mixing in RF systems and a reduction in the usable timing budget in microcontrollers.
Phase noise and jitter are metrics that quantify the frequency stability of a periodic signal. Phase noise defines the noise power spectrum around the fundamental frequency. Jitter metrics quantify the time domain uncertainty in the oscillator period. Ideally, edges of the oscillator signal occur at identical intervals in time. In practical circuits, the edges of the signal deviate from this ideal position in time by some amount each cycle.
The most significant contributing factor to phase noise performance is the quality-factor (Q) of the oscillator circuit. The quality factor is a measure of the loss in a given system, as described by (1):
                    Q        =                  2          ⁢          π          ⁢                                          ⁢                                    W              s                                      W              d                                                          (        1        )            Here, Ws is the energy stored at resonance and Wd is the energy dissipated per cycle. A more commonly used expression for the quality factor of electrical circuits is given by the following:
                    Q        =                              f            o                                BW                          _              ⁢              3              ⁢              dB                                                          (        2        )            where fo is the resonant frequency and BW—3dB is the 3dB bandwidth of the magnitude response.
The relationship between quality factor and phase noise is quadratic, as shown in (3):
                                          (                                          N                o                            C                        )                    fm                =                              FkT            C                    ⁢                      1                          8              ⁢                              Q                2                                              ⁢                                    (                                                f                  o                                                  f                  m                                            )                        2                                              (        3        )            
Here, No/C is the phase noise density at offset fm from fo, F is the noise factor of the circuit, k is Boltzmans's constant, T is temperature, C is the output power, and fo is the nominal output frequency. Clearly, by developing an oscillator with a high Q-factor, the phase noise performance can be enhanced. Moreover, a clear tradeoff between power dissipation and Q can be made to meet high stability and low power oscillator specifications.
The concept of phase noise can be described mathematically. Consider the ideal output of an oscillator circuit, represented mathematically by (4):vo(t)=Vo sin(2πfot)  (4)Vo is the signal amplitude and t is time. The Fourier transform of this function will be an impulse, or Dirac-delta function, in the frequency domain at the frequency fo, as described previously. Now consider the introduction of phase noise. The output signal in the time domain is then described by the following expression:vo(t)=Vo sin(2πfot+φ(t))  (5)where φ(t) represents the phase noise-a stochastic process.
The manner in which arbitrary noise injection translates into phase noise can be understood through examination of Hajimiri's Time-Varying Phase Noise Model. First, consider an ideal LC network. Since the network is lossless, any noise introduced into the circuit will be sustained infinitely. Now, consider an impulse current that is injected into the circuit at some time τ. It is clear that if the impulse occurs at an oscillation peak, the signal becomes amplitude modulated. Thus, the output does not deviate from the initial center frequency, but the amplitude changes indefinitely. However, if the impulse occurs some time between peaks, it is clear that the phase of the oscillation is perturbed. Therefore, noise introduced while the output is in this portion of the cycle will contribute significantly to the phase noise, while noise introduced at the peaks of oscillation will not contribute at all. An impulse sensitivity function (ISF) can be assigned to a given oscillator topology. This function describes the time-domain regions where the oscillator is most sensitive to noise injection, and therefore results in phase noise. A typical LC oscillator is most sensitive to noise at the zero-crossings and least sensitive at the peaks. The corresponding ISF, Γ(ωt), represents this concept.
This relatively straightforward theory can be utilized to explain phase noise performance of a variety of oscillator topologies. For example, ring oscillators are common in low performance digital systems. These oscillators make use of an odd number of inverters in a chain. The ISF is maximized at the zero-crossings and minimized while the output is flat. Upon inspection of the ring oscillator circuit, it is clear that the output signal is flat when one of the devices is off and the other is operated in the linear region. While the devices are in these regions of operation, little noise is coupled to the output. However, while the signal is crossing zero, both devices are on and saturated. Here, the potential for noise injection is maximized since it can originate from either device or either supply rail. Unfortunately, this corresponds to the point where the ISF function is maximized. Thus, this simple analysis clearly indicates the reason why ring oscillators exhibit such poor phase noise performance. Moreover, the design objective of a topology such as this one is to switch the devices as quickly as possible. Thus, the duration of time where the ISF is non-zero is minimized.
LC oscillators do not suffer from this problem. The choice of LC oscillator topology will dictate the phase noise performance since the injection of energy into the tank is highly dependent on the configuration. Given the discussion above, a topology that injects energy while the ISF is minimized and does not inject energy while it is maximized is highly desirable. Many LC configurations approach this performance. For example, in the Colpitts configuration, the active device injects current at the voltage peaks, which corresponds to points where the ISF is low. This is why the Colpitts configuration is so common. The phase noise performance is excellent.
Technologies
Many different technologies for oscillators and clock generation circuits exist, the most prevalent of which is the crystal-based oscillator. Crystals are macroscopic off-chip components that are utilized for their high quality factor and thus high performance in oscillator applications. The majority of electronic systems today utilize a crystal oscillator. The drawbacks of crystals include the fact that they are relatively expensive, large, and cannot be integrated with the transistor electronics. The crystal is typically off-chip and it can occupy a board area that is a substantial fraction of the integrated circuits it supports. In dense embedded applications, this is a significant bottleneck toward miniaturization. Moreover, the cost of these crystals can, in fact, approach the cost of the supported integrated circuit itself.
In low performance applications, on-chip oscillators are commonly utilized because they can be manufactured cheaply and with minimum usage of silicon die area. However, as discussed previously, integrated topologies such as the ring oscillator suffer from very poor phase noise performance. Some of the contributing factors to this can be alleviated with careful design techniques, but even under these conditions, high performance cannot be achieved. Additional integrated topologies include the use of on-chip planar capacitors and inductors to form an LC-tank. Typically, these LC-tanks will provide a reference that is more stable than a ring oscillator, but performance is still poor due to the lack of high quality inductors and capacitors in standard CMOS technology. This can be attributed mostly to loss to the substrate as well as the series resistance in each device. For example, poly-poly capacitors have a very high series resistance and thus the Q is degraded significantly.
MEMS can provide both integration and high performance. A variety of high-Q MEMS components have been demonstrated to date, including MEMS mechanical resonators, resonant cavities, and resonant films, just to name a few.
For embedded microcontroller applications, a crystal is typically used in a phase-locked-loop (PLL) where the low frequency reference is multiplied up from tens of megahertz to hundreds of megahertz or a few gigahertz. A fref is typically generated from a low frequency crystal-based oscillator. The phase detector compares this phase to that of the signal coming from the VCO, which has been divided by the prescalar. After filtering, the VCO is controlled by this output signal. Significant cost, size, and power consumption improvements could be realized if the PLL and crystal oscillator could be replaced with a single, on-chip, high performance, tunable oscillator.
Through the use of a dynamic clock frequency, power savings can be achieved by reducing the clock frequency while low performance operations are executed in the core of the microcontroller. This relationship between dynamic power and frequency is represented by (6):P=αCLVDD2f  (6)
Here, P is the dynamic power dissipation,.α represents the positive switching frequency as a percentage, CL is the load capacitance, VDD is the power supply voltage, and f is the clock frequency. Thus, power and frequency are directly proportional and the ability to tune the clock frequency translates directly into power savings. Additionally, a VCO could be used to over clock the system if an error checker is implemented in the core. Then, the VCO can be tuned to run as fast as possible in very high performance applications.
Much research and development has been underway for some time to integrate a variety of microelectronic components that are currently off-chip. The supporting electronics, such as the crystal, for oscillator circuitry are one of the key areas where integration is yet to be achieved. Here, the motivation for integration is addressed, as well as the challenges associated with integrating oscillators.
Motivation for Integration
The benefits associated with high levels of microelectronic integration are many. First and foremost is cost. The majority of the cost associated with an integrated circuit is in the package for that circuit. Therefore, in any system, if the number of IC components could be reduced, the overall system cost would be reduced dramatically. Also of significant importance is power, especially with the growing importance of portable devices. The power required to transmit signals across a printed circuit board is approximately an order of magnitude larger than the power required to transmit signals internally on an IC. Significant power savings can therefore be obtained through integration at the IC level. Lastly, a major impetus in IC technology recently is size reduction. In many applications, size and weight are paramount. Integration significantly reduces the size of microelectronic systems.
Challenges Associated with Integrating Oscillator Circuits
As described previously, the majority of oscillator circuits utilize quartz crystal technology. In order to be feasible, an integrated solution must provide comparable performance. This is a difficult task since the majority of on-chip integrated oscillators exhibit very poor performance due to the lack of high Q-factor components on-chip.
Also of interest is the fabrication technology. If MEMS is to truly be adopted as a solution for integrated oscillators, it must be simple, cost effective, and truly compatible with CMOS process technology. Several approaches have been adopted to integrate MEMS technology with CMOS. These include a preprocessing MEMS-first approach, such as Sandia's iMEMS process and UC-Berkeley's MICS process, a mixed MEMS and circuits technique, and a post-processing, MEMS-last approach. Most commercial foundries, however, will not accept preprocessed wafers due to concern for contamination of the facility.
SOI Technology
Important differences between a bulk silicon NFET device and an SOI nFET device include the presence of the BOX and the oxide surrounding the SOI device, which provides superior isolation between devices when compared to bulk silicon. Also, the junction capacitance of the SOI device is an order of magnitude less than that of the bulk device which translates directly into higher speed and lower power. Other advantages of SOI technology include reduced short channel effects, due to the shallow source and drain regions of the device. Additionally, SOI devices exhibit better sub-threshold slope, the absence of body effect, improved packing density, and latch-up immunity.
An SOI device may be either fully-depleted (FD) or partially-depleted (PD). When an FD device is on, the body under the gate is fully depleted of charge. However, the threshold voltage of the device is a strong function of the silicon layer thickness and therefore it is difficult to control. Moreover, the source and drain junctions are very shallow and hence the source and drain resistance is high, which is undesirable. Most SOI work to date has been in PD SOI, where the gate depletes only part of the body under it. This technology overcomes the problems associated with FD SOI, but introduces what are known as floating-body effects. These effects can be attributed to the fact that the body of the device is not fully depleted when it is on. As such, these devices exhibit shifts in the threshold voltage as well as hysteretic timing patterns due to charging of the body from impact ionization. Nevertheless, PD SOI has been demonstrated to yield 20–35% improvement in performance over bulk silicon and thus the majority of recent work has been in PD SOI.
CMOS Integration Opportunities
SOI is emerging as the ideal substrate for integration of a variety of technologies. First, the BOX and isolation oxide significantly reduce coupling between devices. Therefore, analog, mixed-signal, digital, and RF electronics can be integrated onto a single chip—a challenge in bulk CMOS due to poor isolation. Moreover, it has been demonstrated that high performance and low cost MEMS devices can be fabricated in SOI. Lastly, the speed and power performance gains realized in SOI make it the emerging substrate of choice for SoC and Microsystem solutions.
Despite the inherent benefits of SOI technology, the vast majority of integrated circuits are currently fabricated in bulk CMOS. Modern bulk processes offer many opportunities to integrate a variety of technologies onto a single chip. For example, Taiwan Semiconductor Manufacturing Company's mixed-mode processes support multiple metal layers for extensive routing, MiM capacitors for analog and RF circuits, and a thick top metal layer for RF devices such as inductors.
MEMS in CMOS
Much previous work has demonstrated MEMS technology where it is claimed that the MEMS devices are compatible with CMOS technology. However, these reported devices all require some specialized processing steps that are substantially different from standard CMOS manufacturing. No previous work has actually demonstrated MEMS devices in a truly standard CMOS manufacturing process along with active transistor electronics in the same process.
MEMS devices in SOI have recently emerged as a topic of great interest. The overall structure of an SOI substrate provides many opportunities for manufacturing MEMS devices with low process complexity. For example, the device layer of an SOI wafer can be utilized as the structural material for a MEMS device. This material is single crystal silicon and thus, the material properties are superior to those of polycrystalline silicon. Moreover, the BOX can be utilized as a built-in release layer for these structures. In fact, suspended, single crystal silicon devices can be fabricated with one mask using this technique. Additionally, the BOX can be used as an etch stop for backside or frontside etching. This is useful for applications where regions of the substrate are to be removed around a device in order to minimize coupling loss.
Low Noise and Weak Inversion Circuits
Weak inversion is the device operation regime in which a MOS device has not been fully inverted. Full inversion occurs when the device gate voltage exceeds the threshold voltage and a channel is induced between the source and drain. For voltages in the range where surface inversion occurs, but less than the threshold voltage, the device is said to be in weak inversion. This area of operation has many interesting properties, the most notable of which enhanced transconductance of the device. The transconductance in this regime is given by the following expression:
                              g          m                =                              I            D                                V            T                                              (        7        )            
Here, ID is the drain current and VT is the thermal voltage. This expression compares to the following expression for devices in strong inversion,
                              g          m                =                              2            ⁢            μ            ⁢                                                  ⁢                          C              ox                        ⁢                          W              L                        ⁢                          I              D                                                          (        8        )            where μ is mobility, Cox is the MOS capacitance, and W and L are the length and width of the device, respectively. Clearly, the transconductance of the device is proportional to the root of ID in strong inversion and is directly proportional to ID in weak inversion. As such, weak inversion is very attractive since the current drive, and thus the gain of the device, can be maximized with the minimum current. Therefore, power consumption can be minimized. In oscillator applications, this approach is highly appropriate because a minimum loop gain is required to start-up the oscillation. With the use of weak inversion techniques, this start-up can be achieved with the minimum power. One of the lowest power VCOs to date has been demonstrated using weak inversion techniques.MEMS LC Components
One of the most common topologies for high performance VCOs is the LC-tank. This is largely due to the fact that LC-tanks can be integrated easily with CMOS technology and the performance of an LC-tank is superior to that of integrated ring oscillators. The performance of the LC-tank is best characterized by its quality factor. LC-tanks with high Q-factors will provide a narrow response and thus be appropriate for stable, high performance oscillators. Therefore, maximizing the quality factor of LC-tanks is a subject of much research.
Much work has been completed to date in the area of micromachined varactors. The simplest topology for such a device is shown in FIGS. 1 and 2. Young and Boser discloses a movable metal top plate, typically aluminum (Al), is suspended over a fixed bottom plate and supported by a mechanical network of arms as shown in FIG. 1. By applying a voltage, VDC, across the device, the movable top plate will deflect some distance x and thus the capacitance of the device is modulated. The varactor serves as the variable device for tuning the VCO.
Recall that capacitance is given by the following relationship:
                    C        =                              ɛ            ⁢                                                  ⁢            A                                x            o                                              (        9        )            where ε is the permitivity of air, A is the plate overlap area, and xo is the nominal distance between the plates. Thus, for the varactor, this expression becomes:
                    C        =                              ɛ            ⁢                                                  ⁢            A                                              x              o                        -            x                                              (        10        )            where x is some displacement forced by the tuning voltage. The electrostatic force generated between the plates by this voltage is given by the following relationship:
                              F          e                =                                            1              2                        ⁢                                          ∂                C                                            ∂                x                                      ⁢                          V              DC              2                                =                                    1              2                        ⁢                                          CV                DC                2                                                              (                                                            x                      o                                        -                    x                                    )                                2                                                                        (        11        )            The effective electrical spring constant is given by (12):
                              k          e                =                                                                        ∂                                  F                  e                                                            ∂                x                                                          =                                    CV              DC              2                                                      (                                                      x                    o                                    -                  x                                )                            2                                                          (        12        )            
A mechanical spring constant, km, is associated with the top plate suspension and a restoring force, Fm, is generated by this suspension. The relationship between km and Fm is given by Hooke's Law.Fm=kmx  (13)The magnitudes of Fm and Fe are equal at equilibrium.
                                          k            m                    ⁢          x                =                                            1              2                        ⁢                                          CV                DC                2                                            (                                                      x                    o                                    -                  x                                )                                              =                                    1              2                        ⁢                                          k                e                            ⁡                              (                                                      x                    o                                    -                  x                                )                                                                        (        14        )            Lastly, the expression for ke in terms of km can written as follows:
                                          k            e                    ⁢          x                =                              2            ⁢                                                  ⁢                          k              m                        ⁢            x                                (                                          x                o                            -              x                        )                                              (        15        )            
When x=xo/3, the two spring constants are equal. Beyond this point, the electrical force exceeds the maximum mechanical restoring force and the plates are pulled together. Thus, the tuning voltage associated with a deflection of x=xo/3 is called the pull-in voltage. It is trivial to show that the theoretical tuning range of this device is then 50%.
In FIG. 2, CTP and CBP represent the parasitic capacitance to the substrate. These parasitic capacitors are what degrade the tuning range as shown in the work by Young and Boser. Typically in an oscillator application, CBP is negligible because the bottom plate and the substrate are both grounded. However, CTP appears in parallel with the tunable capacitor. Moreover, the relatively large tuning voltage is across it. Thus, this device cannot achieve the theoretical tuning range because CTP limits the amount that the total capacitance can be modulated by the deflection of the top plate.
This work was extended by Zou et al. and a tuning range of 69.8% was achieved. The modification they introduced is illustrated in FIG. 3. Here the control voltage is applied across a large gap while the tunable section of the varactor is across a small gap. Though this clever technique has greatly enhanced the tuning range, it is not CMOS compatible.
Yao et al. demonstrated a tuning range of 300% using lateral comb structures which were fabricated using a deep reactive ion etch (DRIE) technique in SOI, but these devices pose integration problems with standard CMOS processing and consequently may not be appropriate for monolithic applications. Table I summarizes previous work in this field.
TABLE ISummary of Previous MEMS Varactor WorkTuningNominalReferenceDeviceRangeCapacitanceQFrequencyYearYoon andParallel plate7.7%1.14pF2911GHz2000NguyenZou et al.Modified69.8% 58fFNANA2000parallel plateYao et al.Comb 300% 1–5pF100400MHz1998Fan et al.SuspendedNA500fFNANA1998parallel plateYoung andParallel plate 16%2pF601GHz1997Boser
A wide variety of high performance integrated inductors have been demonstrated recently using micromachining technology. Many of these devices have achieved a high quality factor. For example, Yeh et al. have demonstrated a copper-encapsulation technique that yielded inductors with Q-factors over 30 at 5 GHz. Yoon et al. have shown a Q-factor of 16.7 at 2.4 GHz using a solenoid structure in electroplated copper.
A key factor in inductor Q performance is loss to the substrate, due to eddy currents, and series resistance in the device material. Because of this, suspended inductors and copper inductors have been a subject of much research. For example, Fan et al. demonstrated a high performance suspended inductor using micromachined hinges that raised the inductor 250 μm over the substrate. A summary of this previous work is shown in Table II.
TABLE IISummary of Previous Integrated Inductor WorkNominalReferenceDeviceCapacitanceQFrequencyYearRogers et al.Cu-plated2.6nH172.5GHz2001Yeh et al.Cu-encapsulated2–12nH305GHz2000Yoon et al.Cu-plated Solenoid2.67nH16.72.4GHz1999Ribas et al.Suspended4.8nH1616GHz1998Fan et al.Suspended24nHNA6.6GHz1998Young et al.3D Cu Coil4.8nH301GHz1997Hisamoto et al.Suspended in SOI7.7nH1119.6GHz1996
Many of these devices pose significant challenges in terms of integration with CMOS technology. In fact, some are not at all compatible with CMOS.
A wide variety of integrated oscillators have been reported. Moreover, many different technologies have been explored in order to achieve fully integrated oscillators. The significant figures of merit for these devices include the power and phase noise performance for each oscillator. Table III summarizes the recent work in the field.
TABLE IIISummary of Recent VCO WorkPhase NoiseReferenceTechnologyDensityPowerFrequencyYearRogers et al.Cu inductors, Bipolar−106dBc/Hz18mW2GHz2001@100kHzSamori et al.Bipolar−104dBc/Hz14mW2.6GHz2001@100kHzDeMuer et al.Planar IC inductor,−125dBc/Hz34.2mW2GHz2000BiCMOS@600kHzDec andMEMS varactor,−126dBc/Hz15mW1.9GHz2000SuyamaBondwire inductor,@600kHzCMOSDec andMEMS varactor,−122dBc/Hz13.5mW2.4GHz2000SuyamaBondwire inductor,@1MHzCMOSKlepser andIntegrated inductor,−129dBc/Hz18mW2.4GHz2000KuceraVaractor diode,@3MHzBiCMOSZannoth et al.Planar IC inductor,−139dBc/Hz29.7mW1.8GHz2000Bipolar@4.7MHzHarada et al.Planar IC inductor,−110dBc/HzNA2GHz2000CMOS/SIMOX@1MHzHung andPlanar IC and bond-−126dBc/Hz12.7mW1.1GHz2000Kennethwire inductor, CMOS@600kHzSvelto et al.MOS varactor,−119dBc/Hz12mW1.3GHz2000Bondwire inductor,@600kHzCMOSYoung et al.MEMS varactor,−105dBc/HzNA1GHz1999CMOS@100kHzZohios et al.Integrated Cu−122dBc/Hz21mW1GHz1999inductor, Diode,@600kHzBiCMOSYoung et al.MEMS varactor, 3D−136dBc/Hz43mW859MHz1998coil inductor, CMOS@3MHzRoessig et al.MEMS resonator,−88dBc/HzNA1.022MHz1998CMOS@500HzCraninckxPlanar IC inductor,−116dBc/Hz6mW1.8GHz1996and SteyaertCMOS@600kHzCraninckxBondwire inductor,−115dBc/Hz28mW1.8GHz1995and SteyaertCMOS@200kHz
Many single-package clock parts are commercially available from companies such as Texas Instruments and distributed by electronics distributors such as Digi-Key. These clocks typically make use of a macroscopic crystal as the time reference for the system. Moreover, these clocks tend to consume significant power. A simple ring oscillator that many circuit design companies use is suitable for only the very lowest performance applications.
Much technology has been developed for radio frequency (RF) applications. Significant contributions in this area are cited in the following section. The focus of these works has been to develop a low phase noise oscillator for cellular communications.